(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method used to form a pocket implant region, with a specific profile, for a N channel metal oxide semiconductor (NMOS), device, to alleviate short channel effects (SCE).
(2) Description of Prior Art
The use of micro-miniaturization, or the ability to fabricate semiconductor devices with sub-micron features, has resulted in improved device performance, as well as reduced process costs, for semiconductor components formed with these reduced dimensions. The use of sub-micron features allow reductions in junction capacitance to be realized, thus improving device performance, while a greater number of smaller semiconductor chips, still offering equivalent or greater device densities than counterparts fabricated with larger dimensions, can now be obtained from a specific size starting substrate, thus reducing the process cost for a specific semiconductor chip. However decreasing device features, although offering improved performance and lower process cost, can in some cases result in unwanted device phenomena, such as short channel effects (SCE), sometimes encountered with narrow channel width devices.
As the width of a gate structure shrinks, allowing performing enhancing, narrow channel lengths to be realized, the depletion region formed at the sourcexe2x80x94substrate interface, approaches the depletion region formed at the other end of the channel region established at the drain-substrate interface. The lower the dopant level of the semiconductor substrate, the greater the extent of the depletion regions. For narrow channel length devices these depletion regions can encroach, and perhaps touch, resulting in unwanted leakages or punch through. In addition the low dopant level of the semiconductor substrate, near the depletion regions, can result in a threshold voltage (Vt), roll-off phenomena, which is described as decreasing Vt values as a function of decreasing channel length. One solution to the punch through and Vt roll-off phenomena is the use of a pocket, or halo region, formed at each end of the narrow channel region, and formed with the same dopant type used in the semiconductor substrate, but at a higher dopant level, in an attempt to reduce the extent of depletion region formation. However if careful fabrication sequences are not employed the pocket region profile can broaden as a result of diffusion occurring during subsequent process steps performed at elevated temperatures, thus reducing the channel length to levels where punch through and VT roll-off phenomena again become prevalent.
This invention will describe a procedure that results in confinement, or reduced movement of the pocket implant region, during subsequent process steps performed at elevated temperatures. Specific anneal procedures applied to pocket implant regions, prior to activation and drive-in of the heavily doped source/drain regions, will result in decreased punch through leakage and Vt roll-off, when compared to counterparts fabricated without the anneal procedures taught in this invention. Prior art, such as Burr et al, in U.S. Pat. No. 5,650,783, describe a pocket implant region, however that prior art does not describe the details of the anneal procedure needed to restrict pocket implant region diffusion.
It is an object of this invention to fabricate a NMOS device, featuring a narrow channel length region.
It is another object of this invention to form an indium pocket implant region, under the lightly doped source/drain region of the NMOS device, to reduce SCE phenomena such as punch through leakage, and Vt roll-off
It is still another object of this invention to perform a low temperature anneal procedure, after an indium pocket implantation procedure, and after a lightly doped source/drain implantation procedure, to reduce broadening of the indium pocket profile via unwanted anomalous diffusion of indium.
In accordance with the present invention a method of fabricating a narrow channel length region, NMOS device, featuring an indium pocket region located under a source/drain region, and subjected to a low temperature anneal procedure to restrict the broadening of the indium pocket profile, is described. After formation of a gate structure, on an underlying gate insulator layer, a first ion implantation procedure is used to form an indium pocket region in an area of a P type, semiconductor substrate, not covered by the gate structure. A second ion implantation is then performed to create an arsenic, lightly doped source/drain region, in a top portion of the indium pocket region. A low temperature anneal procedure is then employed to restrict anomalous diffusion of indium, confining the indium pocket region, followed by an RTA procedure, used to anneal implant damage so that transient enhanced diffusion (TED), will not occur in subsequent process steps such as insulator spacer deposition. Formation of insulator spacers on the sides of the gate structure, is followed by a third ion implantation procedure, used to form a heavily doped, N type source/drain region, in a region of the P type semiconductor substrate not covered by the gate structure or by the insulator spacers. A post source/drain anneal procedure is then performed.